Tim9 Status Register (Timx_Sr) - ST STM32F410 Reference Manual

RM0401
16.4.4

TIM9 status register (TIMx_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to '0'.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
12 11 10 9
Res. CC2OF CC1OF
rc_w0 rc_w0
General-purpose timers (TIM9 and TIM11)
8 7 6
Res. Res. TIF
rc_w0
RM0401 Rev 3
5 4 3 2
Res. Res. Res. CC2IF
rc_w0
1 0
CC1IF UIF
rc_w0 rc_w0
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