ST STM32F410 Reference Manual page 105

RM0401
Bits 17:16 PLLP: Main PLL (PLL) division factor for main system clock
Caution: The software has to set these bits correctly not to exceed 100 MHz on this domain.
Bit 15 Reserved, must be kept at reset value.
Bits 14:6 PLLN: Main PLL (PLL) multiplication factor for VCO
Caution: The software has to set these bits correctly to ensure that the VCO output
Note: Multiplication factors possible for VCO input frequency higher than 1 MHz but care
Bits 5:0 PLLM: Division factor for the main PLL (PLL) input clock
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
Set and cleared by software to control the frequency of the general PLL output clock. These
bits can be written only if PLL is disabled.
PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
00: PLLP = 2
01: PLLP = 4
10: PLLP = 6
11: PLLP = 8
Set and cleared by software to control the multiplication factor of the VCO. These bits can
be written only when PLL is disabled. Only half-word and word accesses are allowed to
write these bits.
frequency is between 100 and 432 MHz. (check also
Dedicated Clocks Configuration Register
VCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432
000000000: PLLN = 0, wrong configuration
000000001: PLLN = 1, wrong configuration
...
000110010: PLLN = 50
...
001100011: PLLN = 99
001100100: PLLN = 100
...
110110000: PLLN = 432
110110001: PLLN = 433, wrong configuration
...
111111111: PLLN = 511, wrong configuration
must be taken to fulfill the minimum VCO output frequency as specified above.
Set and cleared by software to divide the PLL input clock before the VCO. These bits can be
written only when the PLL is disabled.
ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63
000000: PLLM = 0, wrong configuration
000001: PLLM = 1, wrong configuration
000010: PLLM = 2
000011: PLLM = 3
000100: PLLM = 4
...
111110: PLLM = 62
111111: PLLM = 63
(RCC_DCKCFGR))
RM0401 Rev 3
Reset and clock control (RCC)
Section 5.3.17: RCC
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