Figure 117. Control Circuit In Normal Mode, Internal Clock Divided By 1; Figure 118. Ti2 External Clock Connection Example - ST STM32F410 Reference Manual

General-purpose timers (TIM5)
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 117
without prescaler.

Figure 117. Control circuit in normal mode, internal clock divided by 1

External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
352/771
shows the behavior of the control circuit and the upcounter in normal mode,

Figure 118. TI2 external clock connection example

RM0401 Rev 3
RM0401