Fmpi2C Implementation; Fmpi2C Functional Description; Table 84. Stm32F410 Fmpi2C Implementation - ST STM32F410 Reference Manual

RM0401
The following additional features are also available depending on the product
implementation (see
•
SMBus specification rev 3.0 compatibility:
–
–
–
–
–
–
• PMBus rev 1.3 standard compatibility
•
Independent clock: a choice of independent clock sources allowing the FMPI2C
communication speed to be independent from the PCLK reprogramming
22.3

FMPI2C implementation

This manual describes the full set of features implemented in FMPI2C1
7-bit addressing mode
10-bit addressing mode
Standard-mode (up to 100 kbit/s)
Fast-mode (up to 400 kbit/s)
Fast-mode Plus
Independent clock
Wakeup from Stop mode
SMBus/PMBus
1. X = supported.
2. 20 mA output drive for Fm+ mode is not supported.
22.4

FMPI2C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
Section 22.3: FMPI2C
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and Device support
SMBus alert
Timeouts and idle condition detection

Table 84. STM32F410 FMPI2C implementation

I2C features
(2)
(up to 1 Mbit/s)
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
2
C bus.
implementation):
(1)
RM0401 Rev 3
I2C4
X
X
X
X
X
X
-
X
525/771
591