Figure 98. Counter Timing Diagram With Prescaler Division Change From 1 To 2 - ST STM32F410 Reference Manual

General-purpose timers (TIM5)
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 32-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 98
ratio is changed on the fly:

Figure 98. Counter timing diagram with prescaler division change from 1 to 2

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and Figure 99 give some examples of the counter behavior when the prescaler
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