Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr) - ST STM32F410 Reference Manual

RM0401
5.3.13 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0007 7930
Access: no wait state, word, half-word and byte access.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
SYSC
EXTI SPI1
FG
Res.
LPEN LPEN
LPEN
rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Bit 17 Reserved, must be kept at reset value.
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Bit 15 EXTILPEN: System controller and external interrupt clock enable during sleep mode
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
Bits 11:9 Reserved, must be kept at reset value.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
This bit is set and cleared by software
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Set and cleared by software.
0: EXTI clock disabled during Sleep mode
1: EXTI clock enabled during Sleep mode
Set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Set and cleared by software.
0: SPI1 clock disabled during Sleep mode
1: SPI1 clock enabled during Sleep mode
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
ADC1 USART6
Res. Res.
LPEN LPEN
rw rw
RM0401 Rev 3
Reset and clock control (RCC)
20 19 18
SPI5 TIM11
Res.
LPEN LPEN
rw rw
4 3 2
USART1
Res. Res.
LPEN
rw
17 16
TIM9
Res.
LPEN
rw
1 0
TIM1
Res.
LPEN
rw
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