Control Register 1 (Usart_Cr1) - ST STM32F410 Reference Manual

Advanced arm-based 32-bit mcus
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RM0401
Universal synchronous receiver transmitter (USART) /universal asynchronous receiver
24.6.4

Control register 1 (USART_CR1)

Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
OVER8
Res.
UE
rw
rw
Bits 31:16 Reserved, must be kept at reset value
Bit 15 OVER8: Oversampling mode
0: oversampling by 16
1: oversampling by 8
Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes: when
Bit 14 Reserved, must be kept at reset value
Bit 13 UE: USART enable
When this bit is cleared the USART prescalers and outputs are stopped and the end of the
current
byte transfer in order to reduce power consumption. This bit is set and cleared by software.
0: USART prescaler and outputs disabled
1: USART enabled
Bit 12 M: Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, n Stop bit
1: 1 Start bit, 9 Data bits, n Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and reception)
Bit 11 WAKE: Wakeup method
This bit determines the USART wakeup method, it is set or cleared by software.
0: Idle Line
1: Address Mark
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
28
27
26
25
Res.
Res.
Res.
12
11
10
9
M
WAKE
PCE
PS
rw
rw
rw
rw
SCEN=1,IREN=1 or LINEN=1 then OVER8 is forced to '0 by hardware.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
PEIE
TXEIE
TCIE
RXNEIE IDLEIE
rw
rw
rw
RM0401 Rev 3
21
20
19
18
Res.
Res.
Res.
5
4
3
2
TE
RE
rw
rw
rw
rw
17
16
Res.
Res.
1
0
RWU
SBK
rw
rw
673/771
679

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