Hardware Flow Control; Figure 243. Reception Using Dma; Figure 244. Hardware Flow Control Between 2 Usarts - ST STM32F205 series Reference Manual

Advanced arm-based 32-bit mcus

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DMA reads USART_DR

DMA TCIF flag

(Transfer complete)

software configures the

DMA to receive 3 data

blocks and enables

Error flagging and interrupt generation in multibuffer communication

In case of multibuffer communication if any error occurs during the transaction the error flag

will be asserted after the current byte. An interrupt will be generated if the interrupt enable

flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in

case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in

the USART_CR3 register), which if set will issue an interrupt after the current byte with

either of these errors.

Hardware flow control

It is possible to control the serial data flow between 2 devices by using the CTS input and

the RTS output. The

RTS and CTS flow control can be enabled independently by writing respectively RTSE and

CTSE bits to 1 (in the USART_CR3 register).

Universal synchronous asynchronous receiver transmitter (USART)

set by hardware

cleared by DMA read

DMA reads F1

shows how to connect 2 devices in this mode:

RM0033 Rev 8

DMA reads F2

set by hardware

DMA reads F3

The DMA transfer

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