I 2 C Clock Control Register (I2C_Ccr) - ST STM32F410 Reference Manual

RM0401
Bit 2 TRA: Transmitter/receiver
Bit 1 BUSY: Bus busy
– Set by hardware on detection of SDA or SCL low
– cleared by hardware on detection of a Stop condition.
Bit 0 MSL: Master/slave
– Set by hardware as soon as the interface is in Master mode (SB=1).
– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was
set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found
set in I2C_SR1 or when the STOPF bit is cleared.
2
23.6.8 I C Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note: f must be at least 2 MHz to achieve Sm mode I²C frequencies. It must be at least 4
PCLK1
MHz to achieve Fm mode I²C frequencies. It must be a multiple of 10MHz to reach the
400 kHz maximum I²C Fm mode clock.
The CCR register must be configured only when the I2C is disabled (PE = 0).
15 14 13
F/S DUTY Res. Res.
rw rw
Bit 15 F/S: I2C master mode selection
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on the R/W bit of the address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start
condition, loss of bus arbitration (ARLO=1), or when PE=0.
0: No communication on the bus
1: Communication ongoing on the bus
It indicates a communication in progress on the bus. This information is still updated when
the interface is disabled (PE=0).
0: Slave Mode
1: Master Mode
(ARLO=1), or by hardware when PE=0.
12 11 10 9
rw rw rw
0: Sm mode I2C
1: Fm mode I2C
Inter-integrated circuit (I
8 7 6
CCR[11:0]
rw rw rw
RM0401 Rev 3
5 4 3 2
rw rw rw rw
2
C) interface
1 0
rw rw
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