I 2 S Slave Mode - ST STM32F410 Reference Manual

RM0401
b)
c)
•
For all other combinations of DATLEN and CHLEN, whatever the audio mode selected
through the I2SSTD bits, carry out the following sequence to switch off the I
a)
b)
c)
Note: The BSY flag is kept low during transfers.
2
25.6.6 I S slave mode
For the slave configuration, the I
The operating mode is following mainly the same rules as described for the I
configuration. In slave mode, there is no clock to be generated by the I
clock and WS signals are input from the external master connected to the I
There is then no need, for the user, to configure the clock.
The configuration steps to follow are listed below:
1. Set the I2SMOD bit in the SPIx_I2SCFGR register to select I
2
I S standard through the I2SSTD[1:0] bits, the data length through the DATLEN[1:0]
bits and the number of bits per channel for the frame configuring the CHLEN bit. Select
also the mode (transmission or reception) for the slave through the I2SCFG[1:0] bits in
SPIx_I2SCFGR register.
2. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPIx_CR2 register.
3. The I2SE bit in SPIx_I2SCFGR register must be set.
Transmission sequence
The transmission sequence begins when the external master device sends the clock and
when the NSS_WS signal requests the transfer of data. The slave has to be enabled before
the external master starts the communication. The I
the master initiates the communication.
2
For the I
data register corresponds to the data for the left channel. When the communication starts,
the data are transferred from the Tx buffer to the shift register. The TXE flag is then set in
order to request the right channel data to be written into the I
The CHSIDE flag indicates which channel is to be transmitted. Compared to the master
transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the
external master. This means that the slave needs to be ready to transmit the first data
before the clock is generated by the master. WS assertion corresponds to left channel
transmitted first.
Note: The I2SE has to be written at least two PCLK cycles before the first clock of the master
comes on the CK line.
The data half-word is parallel-loaded into the 16-bit shift register (from the internal bus)
during the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first.
The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt
is generated if the TXEIE bit in the SPIx_CR2 register is set.
2
Then wait 1 I S clock cycle (using a software loop)
2
Disable the I S (I2SE = 0)
Wait for the second to last RXNE = 1 (n – 1)
2
Then wait one I S clock cycle (using a software loop)
2
Disable the I S (I2SE = 0)
S, MSB justified and LSB justified modes, the first data item to be written into the
Serial peripheral interface/ inter-IC sound (SPI/I2S)
2
S can be configured in transmission or reception mode.
2
S data register has to be loaded before
RM0401 Rev 3
2
S:
2
S master
2
S interface. The
2
S interface.
2
S mode and choose the
2
S data register.
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