Table 20. Stop Mode Entry And Exit - ST STM32F410 Reference Manual

RM0401
Section 20.3
•
Real-time clock (RTC): this is configured by the RTCEN bit in the
Backup domain control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
Section 5.3.15: RCC clock control & status register
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Section 5.3.14: RCC Backup domain control register
The ADC can also consume power during the Stop mode, unless it is disabled before
entering it. To disable it, the ADON bit in the ADC_CR2 register must be written to 0.
Note: If the application needs to disable the external clock before entering Stop mode, the HSEON
bit must first be disabled and the system clock switched to HSI.
Otherwise, if the HSEON bit is kept enabled while the external clock (external oscillator) can
be removed before entering stop mode, the clock security system (CSS) feature must be
enabled to detect any external oscillator failure and avoid a malfunction behavior when
entering stop mode.
Exiting Stop mode
The Stop mode is exited according to
Refer to
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
If the code is executed from internal SRAM while the Flash memory in low-power mode, the
Stop wakeup time is reduced since the code execution restarts from SRAM which is directly
available when the clocks are stable.
Stop mode
Mode entry
in Section 20: Independent watchdog
Table 20 for more details on how to exit Stop mode.

Table 20. Stop mode entry and exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP bit is set in Cortex
– PDDS bit is cleared in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR
– No interrupt (for WFI) or event (for WFE) is pending
On Return from ISR:
– SLEEPDEEP bit is set in Cortex
– SLEEPONEXIT = 1
– PDDS bit is cleared in Power Control register (PWR_CR)
– No interrupt is pending
Note: To enter Stop mode, all EXTI Line pending bits (in
(EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm
(Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time
stamp flags, must be reset. Otherwise, the Stop mode entry
procedure is ignored and program execution continues.
Section : Exiting low-power
Description
RM0401 Rev 3
Power controller (PWR)
(IWDG).
Section 5.3.14: RCC
(RCC_CSR).
(RCC_BDCR).
mode.
®
-M4 with FPU System Control register
®
-M4 with FPU System Control register
Pending register
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