Boot Configuration; Table 2. Boot Modes; Table 3. Embedded Bootloader Interfaces - ST STM32F410 Reference Manual

RM0401
2.6

Boot configuration

Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed
through the ICode/DCode buses) while the data area (SRAM) starts from address
0x2000 0000 (accessed through the system bus). The Cortex
fetches the reset vector on the ICode bus, which implies to have the boot space available
only in the code area (typically, Flash memory). STM32F4xx microcontrollers implement a
special mechanism to be able to boot from other memories (like the internal SRAM).
In the STM32F410, three different boot modes can be selected through the BOOT[1:0] pins
as shown in
Boot mode selection pins
BOOT1
x
0
1
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It
is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot
mode.
BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been
sampled, the corresponding GPIO pin is free and can be used for other purposes.
The BOOT pins are also resampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode. After this startup delay is over, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.
Note: When the device boots from SRAM, in the application initialization code, you have to
relocate the vector table in SRAM using the NVIC exception table and the offset register.
Embedded bootloader
The embedded bootloader mode is used to reprogram the Flash memory using interfaces
that depend on the package (refer to
Package USART1
WLCSP36 X
UFQFPN48 PA9/PA10
LQFP64 PA9/PA10
UFBGA64 PA9/PA10
Table 2.
Boot mode
BOOT0
0 Main Flash memory Main Flash memory is selected as the boot space
1 System memory
1 Embedded SRAM

Table 3. Embedded bootloader interfaces

USART2 I2C1
PA2/PA3 PB6/PB7
PA2/PA3 PB6/PB7
PA2/PA3 PB6/PB7 PB10/PB11
PA2/PA3 PB6/PB7 PB10/PB11
RM0401 Rev 3

Table 2. Boot modes

System memory is selected as the boot space
Embedded SRAM is selected as the boot space
Table 3):
I2C2 I2C4 FM+
X PB10/PB3
X PB14/PB15
PB14/PB15
PB14/PB15
®
-M4 with FPU CPU always
Aliasing
SPI1 SPI3
PA15/PA5/
X
PB4/PB5
PA4/PA5/
X
PA6/PA7
PA4/PA5/ PB12/PB13/
PA6/PA7 PC2/PC3
PA4/PA5/ PB12/PB13/
PA6/PA7 PC2/PC3
43/771
44