Figure 204. Bus Transfer Diagrams For Smbus Slave Receiver (Sbc=1) - ST STM32F410 Reference Manual

RM0401
This section is relevant only when SMBus feature is supported. Refer to
FMPI2C
In addition to FMPI2C master transfer management (refer to
master mode) some additional software flowcharts are provided to support SMBus.
SMBus Master transmitter
When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts is NBYTES-1. So if the PECBYTE bit is
set when NBYTES=0x1, the content of the FMPI2C_PECR register is automatically
transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
must be selected (AUTOEND=1). In this case, the STOP condition automatically follows the
PEC transmission.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface

Figure 204. Bus transfer diagrams for SMBus slave receiver (SBC=1)

implementation.
RM0401 Rev 3
Section 22.3:
Section 22.4.9: FMPI2C
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