Repetition Counter; Figure 67. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 68. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32F410 Reference Manual

Advanced-control timers (TIM1)

Figure 67. Counter timing diagram, update event with ARPE=1 (counter underflow)

Figure 68. Counter timing diagram, update event with ARPE=1 (counter overflow)

14.3.3

Repetition counter

Section 14.3.1: Time-base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
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describes how the update event (UEV) is generated with
RM0401 Rev 3
RM0401