Fmpi2C Interrupt And Status Register (Fmpi2C_Isr) - ST STM32F410 Reference Manual

RM0401
22.7.7

FMPI2C interrupt and status register (FMPI2C_ISR)

Address offset: 0x18
Reset value: 0x0000 0001
Access: No wait states
31 30 29
Res. Res. Res. Res.
15 14 13
TIME
BUSY Res. ALERT
OUT
r r
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:17 ADDCODE[6:0]: Address match code (Slave mode)
Bit 16 DIR: Transfer direction (Slave mode)
Bit 15 BUSY: Bus busy
Bit 14 Reserved, must be kept at reset value.
Bit 13 ALERT: SMBus alert
Note: This bit is cleared by hardware when PE=0.
Bit 12 TIMEOUT: Timeout or t
Note: This bit is cleared by hardware when PE=0.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
28 27 26 25
Res. Res. Res.
12 11 10 9
PEC
OVR ARLO
ERR
r r r r
These bits are updated with the received address when an address match event occurs
(ADDR = 1).
In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2
MSBs of the address.
This flag is updated when an address match event occurs (ADDR=1).
0: Write transfer, slave enters receiver mode.
1: Read transfer, slave enters transmitter mode.
This flag indicates that a communication is in progress on the bus. It is set by hardware
when a START condition is detected. It is cleared by hardware when a STOP condition is
detected, or when PE=0.
This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1
and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by
setting the ALERTCF bit.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Refer to Section 22.3: FMPI2C
LOW
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared
by software by setting the TIMEOUTCF bit.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Refer to Section 22.3: FMPI2C
24 23 22
Res.
r r
8 7 6
BERR TCR TC STOPF NACKF ADDR
r r r
implementation.
detection flag
implementation.
RM0401 Rev 3
21 20 19 18
ADDCODE[6:0]
r r r r
5 4 3 2
RXNE
r r r r
17 16
DIR
r r
1 0
TXIS TXE
rs rs
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