ST STM32F410 Reference Manual page 124

Reset and clock control (RCC)
Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode
Set and cleared by software.
0: SPI2 clock disabled during Sleep mode
1: SPI2 clock enabled during Sleep mode
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode
Set and cleared by software.
0: Window watchdog clock disabled during sleep mode
1: Window watchdog clock enabled during sleep mode
Bit 10 RTCAPBLPEN: RTC APB clock enable during Sleep mode
Set and cleared by software.
0: RTC watchdog clock disabled during sleep mode
1: RTC watchdog clock enabled during sleep mode
Bit 9 LPTIM1LPEN: LPTIM1 clock enable during Sleep mode
Set and cleared by software.
0: LPTIM1 clock disabled during sleep mode
1: LPTIM1 clock enabled during sleep mode
Bits 8:5 Reserved, must be kept at reset value.
Bit 4 TIM6LPEN: TIM6 clock enable during Sleep mode
Set and cleared by software.
0: TIM6 clock disabled during Sleep mode
1: TIM6 clock enabled during Sleep mode
Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode
Set and cleared by software.
0: TIM5 clock disabled during Sleep mode
1: TIM5 clock enabled during Sleep mode
Bits 2:0 Reserved, must be kept at reset value.
124/771 RM0401 Rev 3
RM0401