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Debug support (DBG)
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:25
Reserved, must be kept at reset value.
Bit 24 DBG_I2CFMP_SMBUS_TIMEOUT: FMPI2C SMBUS timeout mode stopped when Core is
halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 23 DBG_I2C3_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13
Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted
Bit 11 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
Bit 10 DBG_RTC_STOP: RTC stopped when Core is halted
0: The RTC counter clock continues even if the core is halted
1: The RTC counter clock is stopped when the core is halted
Bits 9:5
Reserved, must be kept at reset value.
754/771
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
rw
rw
rw
24
23
22
Res.
rw
rw
8
7
6
Res.
Res.
Res.
RM0401 Rev 3
21
20
19
18
Res.
Res.
Res.
rw
5
4
3
2
Res.
Res.
rw
rw
RM0401
17
16
Res.
Res.
1
0
Res.
Res.
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