Figure 262. Reception Using Dma; Figure 263. Hardware Flow Control Between 2 Usarts - ST STM32L0x3 Reference Manual

Universal synchronous/asynchronous receiver transmitter (USART/UART)
TX line
RXNE flag
DMA request
USART_RDR
DMA reads
USART_RDR
DMA TCIF flag
(transfer complete)
Software configures the
DMA to receive 3 data
blocks and enables
the USART
Error flagging and interrupt generation in multibuffer communication
In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.
29.5.16 RS232 hardware flow control and RS485 driver enable
using USART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The
802/1043

Figure 262. Reception using DMA

Frame 1
Set by hardware
cleared by DMA read
F1
DMA reads F1
from USART_RDR
Figure 263 shows how to connect 2 devices in this mode:

Figure 263. Hardware flow control between 2 USARTs

USART 1
TX
TX circuit
CTS
RX
RX circuit
RTS
RM0367 Rev 7
Frame 2
F2
DMA reads F2 DMA reads F3
from USART_RDR from USART_RDR
RTS
CTS
Frame 3
Set by hardware
The DMA transfer
is complete
(TCIF=1 in
DMA_ISR)
USART 2
RX
RX circuit
TX
TX circuit
RM0367
F3
Cleared
by
software
ai17193c
MSv31169V2