Figure 65. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 66. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F410 Reference Manual

RM0401 Advanced-control timers (TIM1)

Figure 65. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 66. Counter timing diagram, internal clock divided by N

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