Fast Conversion Mode; Data Management; Using The Dma; Table 46. External Trigger For Injected Channels - ST STM32F410 Reference Manual

RM0401
Table 46
TIM1_CH4 event
TIM1_TRGO event
TIM5_CH4 event
TIM5_TRGO event
Not used
Not used
Not used
EXTI line15
Software source trigger events can be generated by setting SWSTART (for regular
conversion) or JSWSTART (for injected conversion) in ADC_CR2.
A regular group conversion can be interrupted by an injected trigger.
Note: The trigger selection can be changed on the fly. However, when the selection changes,
there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.
This is to avoid spurious detection during transitions.
11.7

Fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are
used to select the number of bits available in the data register. The minimum conversion
time for each resolution is then as follows:
•
12 bits: 3 + 12 = 15 ADCCLK cycles
•
10 bits: 3 + 10 = 13 ADCCLK cycles
•
8 bits: 3 + 8 = 11 ADCCLK cycles
•
6 bits: 3 + 6 = 9 ADCCLK cycles
11.8

Data management

11.8.1

Using the DMA

Since converted regular channel values are stored into a unique data register, it is useful to
use DMA for conversion of more than one regular channel. This avoids the loss of the data
already stored in the ADC_DR register.
When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each
conversion of a regular channel, a DMA request is generated. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.
Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an
interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and
gives the possible external trigger for injected conversion.

Table 46. External trigger for injected channels

Source Connection type
Internal signal from on-chip
timers
External pin
RM0401 Rev 3
Analog-to-digital converter (ADC)
JEXTSEL[3:0]
0000
0001
1010
1011
1100
1101
1110
1111
225/771
242