Data Transfer; Figure 181. Data Reception - ST STM32F410 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
22.4.7

Data transfer

The data transfer is managed through transmit and receive data registers and a shift
register.
Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is
received), the shift register is copied into FMPI2C_RXDR register if it is empty (RXNE=0). If
RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line
is stretched low until FMPI2C_RXDR is read. The stretch is inserted between the 8th and
9th SCL pulse (before the Acknowledge pulse).
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Figure 181. Data reception

RM0401 Rev 3
RM0401