Lptim Register Map; Table 77. Lptim Register Map And Reset Values - ST STM32F410 Reference Manual

Low-power timer (LPTIM)
18.7.10

LPTIM register map

The following table summarizes the LPTIM registers.
Offset Register name
LPTIM_ISR
0x000
Reset value
LPTIM_ICR
0x004
Reset value
LPTIM_IER
0x008
Reset value
LPTIM_CFGR
0x00C
Reset value
LPTIM_CR
0x010
Reset value
LPTIM_CMP
0x014
Reset value
LPTIM_ARR
0x018
Reset value
LPTIM_CNT
0x01C
Reset value
LPTIM_OR
0x020
Reset value
1. If LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
implementation.
Refer to
472/771

Table 77. LPTIM register map and reset values

0 0 0 0 0 0 0 0
Section 2.2 on page 41
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0401 Rev 3
RM0401
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0
CMP[15:0]
ARR[15:0]
CNT[15:0]
Section 18.3: LPTIM
0 0 0
0 0