Table 1. Register Boundary Addresses - ST STM32F410 Reference Manual

RM0401
All the memory map areas that are not allocated to on-chip memories and peripherals are
considered "Reserved". For the detailed mapping of available memory and register areas,
refer to the following table.
The following table gives the boundary addresses of the peripherals available in the
devices.
Cortex
AHB1

Table 1. Register boundary addresses

Bus Boundary address
- 0xE010 0000 - 0xFFFF FFFF
®
-M4 0xE000 0000 - 0xE00F FFFF
- 0x5000 0000 - 0xDFFF FFFF
0x4008 0400 - 0x4FFF FFFF
0x4008 0000 - 0x4008 03FF
0x4002 6800 - 0x4007 FFFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0x4002 5000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0x4002 3400 - 0x4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2800 - 0x4002 2FFF
0x4002 2400 - 0x4002 27FF
0x4002 2000 - 0x4002 23FF
0x4002 1C00 - 0x4002 1FFF
0x4002 0C00 - 0x4002 1BFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
RM0401 Rev 3
Peripheral
Reserved
Cortex-M4 internal peripherals
Reserved
Reserved
RNG
Reserved
DMA2
DMA1
Reserved
Flash interface register
RCC
Reserved
CRC
Reserved
LPTIM1
Reserved
GPIOH
Reserved
GPIOC
GPIOB
GPIOA
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