Adc Regular Sequence Register 1 (Adc_Sqr1) - ST STM32F410 Reference Manual

Analog-to-digital converter (ADC)
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Note: The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
11.12.9

ADC regular sequence register 1 (ADC_SQR1)

Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
SQ16_0 SQ15[4:0]
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0]: Regular channel sequence length
Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
236/771
11 10 9
rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
These bits are written by software with the channel number (0..18) assigned as the 16th in
the conversion sequence.
8 7 6
LT[11:0]
rw rw rw
24 23 22
Res. L[3:0]
rw rw
8 7 6
SQ14[4:0]
rw rw rw
RM0401 Rev 3
5 4 3 2
rw rw rw rw
21 20 19 18
SQ16[4:1]
rw rw rw rw
5 4 3 2
SQ13[4:0]
rw rw rw rw
RM0401
1 0
rw rw
17 16
rw rw
1 0
rw rw