Lptim Compare Register (Lptim_Cmp) - ST STM32F410 Reference Manual

RM0401
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 CNTSTRT: Timer start in Continuous mode
This bit is set by software and cleared by hardware.
In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode.
If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in
Continuous mode as soon as an external trigger is detected.
If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next
match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting
in Continuous mode.
This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
Bit 1 SNGSTRT: LPTIM start in Single mode
This bit is set by software and cleared by hardware.
In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in single pulse mode.
If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in
single pulse mode as soon as an external trigger is detected.
If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the
following match between LPTIM_ARR and LPTIM_CNT registers.
This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
Bit 0 ENABLE: LPTIM enable
The ENABLE bit is set and cleared by software.
0:LPTIM is disabled
1:LPTIM is enabled
18.7.6

LPTIM compare register (LPTIM_CMP)

Address offset: 0x014
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CMP[15:0]: Compare value
CMP is the compare value used by the LPTIM.
Caution: The LPTIM_CMP register must only be modified when the LPTIM is enabled (ENABLE bit
set to '1').
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
rw rw rw rw
RM0401 Rev 3
23 22 21
Res. Res. Res.
7 6 5
CMP[15:0]
rw rw rw
Low-power timer (LPTIM)
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
rw rw rw rw
16
Res.
0
rw
469/771
472