Tim9 Interrupt Enable Register (Timx_Dier); Table 65. Timx Internal Trigger Connections - ST STM32F410 Reference Manual

General-purpose timers (TIM9 and TIM11)
Slave TIM
TIM5
TIM9
16.4.3

TIM9 Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:7
Bit 6 TIE: Trigger interrupt enable
Bits 5:3
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
Bit 0 UIE: Update interrupt enable
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Table 65. TIMx internal trigger connections

ITR0 (TS = '000')
Reserved
Reserved
12 11 10 9
Res. Res. Res.
Reserved, must be kept at reset value.
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Reserved, must be kept at reset value.
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
0: Update interrupt disabled.
1: Update interrupt enabled.
ITR1 (TS = '001')
LPTIM
LPTIM
8 7 6
Res. Res. TIE
rw
RM0401 Rev 3
ITR2 (TS = '010') ITR3 (TS = '011')
Reserved
Reserved
5 4 3 2
Res. Res. Res. CC2IE
rw
RM0401
Reserved
TIM11
1 0
CC1IE UIE
rw rw