Channel Selection; Table 29. Dma1 Request Mapping; Figure 24. Channel Selection - ST STM32F410 Reference Manual

Direct memory access controller (DMA)
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.
8.3.4

Channel selection

Each stream is associated with a DMA request that can be selected out of 8 possible
channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR
register.
The 8 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently
connected to each channel and their connection depends on the product implementation.
Table 29
Peripheral
Stream 0
requests
Channel 0 -
Channel 1 I2C1_RX
Channel 2 -
Channel 3 -
Channel 4 -
Channel 5 -
TIM5_CH3
Channel 6
TIM5_UP
Channel 7 I2C4_RX
166/771

Figure 24. Channel selection

and Table 30 give examples of DMA request mappings.

Table 29. DMA1 request mapping

Stream 1 Stream 2
I2C1_TX -
- -
I2C4_TX -
- -
- -
- -
TIM5_CH4
TIM5_CH1
TIM5_TRIG
TIM6_UP I2C2_RX
Stream 3 Stream 4
SPI2_RX SPI2_TX
I2C4_RX -
- -
- -
- -
- -
TIM5_CH4
TIM5_CH2
TIM5_TRIG
I2C2_RX -
RM0401 Rev 3
Stream 5 Stream 6
- -
I2C1_RX I2C1_TX
- -
- -
USART2_RX USART2_TX
- -
- TIM5_UP
DAC1 DAC2
RM0401
Stream 7
-
I2C1_TX
-
-
I2C4_TX
-
USART2_RX
I2C2_TX