Procedure For Disabling The Spi; Figure 248. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers - ST STM32F410 Reference Manual

RM0401
Figure 248. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
25.3.10

Procedure for disabling the SPI

When SPI is disabled, it is mandatory to follow the disable procedures described in this
paragraph. It is important to do this before the system enters a low-power mode when the
peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some
modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops
providing data for transmission. In this case, the clock stops after the last data transaction.
Standard disable procedure is based on pulling BSY status together with TXE flag to check
if a transmission session is fully completed. This check can be done in specific cases, too,
when it is necessary to identify the end of ongoing transactions, for example:
•
When NSS signal is managed by an arbitrary GPIO toggle and the master has to
provide proper end of NSS pulse for slave, or
•
When transactions' streams from DMA are completed while the last data frame or CRC
frame transaction is still ongoing in the peripheral bus.
The correct disable procedure is (except when receive-only mode is used):
1. Wait until RXNE=1 to receive the last data.
2. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.
3. Read received data.
RXONLY=0) in the case of continuous transfers
RM0401 Rev 3
Serial peripheral interface/ inter-IC sound (SPI/I2S)
695/771
731