ST STM32F410 Reference Manual page 30

List of figures
Figure 99. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 343
Figure 100. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 101. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 102. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 103. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 104. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 345
Figure 105. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 346
Figure 106. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 107. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 108. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 109. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 110. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 111. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 349
Figure 112. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 113. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 350
Figure 114. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 115. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 351
Figure 116. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 351
Figure 117. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 118. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 119. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 120. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 354
Figure 121. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 122. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 123. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 124. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 125. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 126. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 127. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 128. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 365
Figure 129. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 365
Figure 130. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 131. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
Figure 132. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Figure 133. General-purpose timer block diagram (TIM9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 134. General-purpose timer block diagram (TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Figure 135. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 394
Figure 136. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 394
Figure 137. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 138. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Figure 139. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Figure 140. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Figure 141. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Figure 142. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Figure 143. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 398
Figure 144. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 145. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 146. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 400
Figure 147. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 148. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 401
30/771 RM0401 Rev 3
RM0401