Dma Stream X Fifo Control Register (Dma_Sxfcr) - ST STM32F410 Reference Manual

Direct memory access controller (DMA)
Bits 31:0 M1A[31:0]: memory 1 address (used in case of double-buffer mode)
8.5.10

DMA stream x FIFO control register (DMA_SxFCR)

Address offset: 0x24 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0021
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 FEIE: FIFO error interrupt enable
Bit 6 Reserved, must be kept at reset value.
Bits 5:3 FS[2:0]: FIFO status
Bit 2 DMDIS: direct mode disable
192/771
Base address of memory area 1 from/to which the data is read/written.
This register is used only for the double-buffer mode.
These bits are write-protected. They can be written only if:
– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
– the stream is enabled (EN='1' in DMA_SxCR register) and bit CT = '0' in the
DMA_SxCR register.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
This bit is set and cleared by software.
0: FE interrupt disabled
1: FE interrupt enabled
These bits are read-only.
000: 0 < fifo_level < 1/4
001: 1/4 ≤ fifo_level < 1/2
010: 1/2 ≤ fifo_level < 3/4
011: 3/4 ≤ fifo_level < full
100: FIFO is empty
101: FIFO is full
others: no meaning
These bits are not relevant in the direct mode (DMDIS bit is zero).
This bit is set and cleared by software. It can be set by hardware.
0: direct mode enabled
1: direct mode disabled
This bit is protected and can be written only if EN is '0'.
This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in
DMA_SxCR are "10") and the EN bit in the DMA_SxCR register is '1' because the direct
mode is not allowed in the memory-to-memory configuration.
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. FEIE Res.
rw r
RM0401 Rev 3
20 19 18
Res. Res. Res.
4 3 2
FS[2:0] DMDIS
r r rw
RM0401
17 16
Res. Res.
1 0
FTH[1:0]
rw rw