Lptim1 Option Register (Lptim1_Or) - ST STM32F410 Reference Manual

RM0401
18.7.9

LPTIM1 option register (LPTIM1_OR)

Address offset: 0x020
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 OR_1/0: Low-power timer input 1 remap
These bits are set and cleared by software.
00: LPTIM1 input 1 connected to PB5 (AF1) or PC0 (AF1) for timer input
01: LPTIM1 input 1 is connected to PA4, the input signal depends on the alternate function that has
been selected for PA4
10: LPTIM1 input 1 is connected to PB9, the input signal depends on the alternate function that has
been selected for PB9
11: LPTIM1 input 1 is connected to TIM6/DAC trigger
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0401 Rev 3
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res. Res.
Low-power timer (LPTIM)
19 18 17
Res. Res. Res.
3 2 1
Res. Res. OR_1
rw
471/771
16
Res.
0
OR_0
rw
472