RM0401
18.6
LPTIM interrupts
The following events generate an interrupt/wake-up event, if they are enabled through the
LPTIM_IER register:
•
Compare match
•
Auto-reload match (whatever the direction if encoder mode)
•
External trigger event
•
Autoreload register write completed
•
Compare register write completed
•
Direction change (encoder mode), programmable (up / down / both).
Note:
If any bit in the LPTIM_IER register (Interrupt Enable Register) is set after that its
corresponding flag in the LPTIM_ISR register (Status Register) is set, the interrupt is not
asserted.
Interrupt event
Compare match
Auto-reload match
External trigger event
Auto-reload register
update OK
Compare register
update OK
Direction change
18.7
LPTIM registers
18.7.1
LPTIM interrupt and status register (LPTIM_ISR)
Address offset: 0x000
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Interrupt flag is raised when the content of the Counter register
(LPTIM_CNT) matches the content of the compare register (LPTIM_CMP).
Interrupt flag is raised when the content of the Counter register
(LPTIM_CNT) matches the content of the Auto-reload register
(LPTIM_ARR).
Interrupt flag is raised when an external trigger event is detected
Interrupt flag is raised when the write operation to the LPTIM_ARR register
is complete.
Interrupt flag is raised when the write operation to the LPTIM_CMP register
is complete.
Used in Encoder mode. Two interrupt flags are embedded to signal
direction change:
– UP flag signals up-counting direction change
– DOWN flag signals down-counting direction change.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Table 76. Interrupt events
Description
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
DOWN
r
RM0401 Rev 3
Low-power timer (LPTIM)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
ARRO
CMP
EXTTR
UP
K
OK
IG
r
r
r
r
17
16
Res.
Res.
1
0
ARRM
CMPM
r
r
461/771
472
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