Swj Debug Port Pins; Flexible Swj-Dp Pin Assignment; Table 129. Swj Debug Port Pins; Table 130. Flexible Swj-Dp Pin Assignment - ST STM32F410 Reference Manual

RM0401
26.4.1

SWJ debug port pins

Five pins are used as outputs from the STM32F410 for the SWJ-DP as alternate functions
of general-purpose I/Os. These pins are available on all packages.
SWJ-DP pin name
JTMS/SWDIO
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
26.4.2

Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32F410 MCUs offers the possibility of disabling some or all of the SWJ-
DP ports and so, of releasing the associated pins for general-purpose IO (GPIO) usage. For
more details on how to disable SWJ-DP port pins, please refer to
multiplexer and
.
Full SWJ (JTAG-DP + SW-DP) - Reset State
Full SWJ (JTAG-DP + SW-DP) but without NJTRST
JTAG-DP Disabled and SW-DP Enabled
JTAG-DP Disabled and SW-DP Disabled
Note: When the APB bridge write buffer is full, it takes one extra APB cycle when writing the
GPIO_AFR register. This is because the deactivation of the JTAGSW pins is done in two
cycles to guarantee a clean level on the nTRST and TCK input signals of the core.
• Cycle 1: the JTAGSW input signals to the core are tied to 1 or 0 (to 1 for nTRST, TDI
and TMS, to 0 for TCK)
•
Cycle 2: the GPIO controller takes the control signals of the SWJTAG IO pins (like
controls of direction, pull-up/down, Schmitt trigger activation, etc.).

Table 129. SWJ debug port pins

JTAG debug port
Type Description
JTAG Test Mode
I
Selection
I JTAG Test Clock
I JTAG Test Data Input
O JTAG Test Data Output
I JTAG Test nReset
mapping.

Table 130. Flexible SWJ-DP pin assignment

Available debug ports
RM0401 Rev 3
Debug support (DBG)
SW debug port
Type Debug assignment
Serial Wire Data
IO
Input/Output
I Serial Wire Clock
- -
TRACESWO if async trace
-
is enabled
- -
Section 6.3.2: I/O pin
SWJ IO pin assigned
PA13 / PA14 /
PA15 /
JTMS / JTCK /
JTDI
SWDIO SWCLK
X X X
X X X
X X
Released
Pin
assign
ment
PA13
PA14
PA15
PB3
PB4
PB3 / PB4 /
JTDO NJTRST
X X
X
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