ST STM32F410 Reference Manual page 339

RM0401
Offset Register
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
TIMx_BDTR
0x44
Reset value
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
Refer to
Table 60. TIM1 register map and reset values (continued)
Section 2.2 on page 41
0 0
0 0
0 0
0 0
0 0
0 0
for the register boundary addresses.
RM0401 Rev 3
Advanced-control timers (TIM1)
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
LOCK
[1:0]
0 0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
DT[7:0]
0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0
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