Figure 125. Edge-Aligned Pwm Waveforms (Arr=8) - ST STM32F410 Reference Manual

General-purpose timers (TIM5)
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to
Upcounting mode on page
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at '1.
If the compare value is 0 then OCxREF is held at '0.
PWM waveforms in an example where TIMx_ARR=8.
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
Downcounting mode on page
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at '1'. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
'00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
360/771
343.

Figure 125. Edge-aligned PWM waveforms (ARR=8)

346.
RM0401 Rev 3
Figure 125 shows some edge-aligned
RM0401
Section :
Section :