ST STM32F410 Reference Manual page 89

RM0401
Bit 8 EWUP1: Enable WKUP1 pin (PA0)
This bit is set and cleared by software.
0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not
wakeup the device from Standby mode.
1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP1 pin wakes up the system from Standby mode).
Note: This bit is reset by a system reset.
Bit 7 EWUP2: Enable WKUP2 pin (PC0)
This bit is set and cleared by software.
0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not
wakeup the device from Standby mode.
1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP2 pin wakes up the system from Standby mode).
Note: This bit is reset by a system reset.
Bit 6 EWUP3: Enable WKUP3 pin (PC1)
This bit is set and cleared by software.
0: WKUP3 pin is used for general purpose I/O. An event on the WKUP3 pin does not
wakeup the device from Standby mode.
1: WKUP3 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP3 pin wakes up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 BRR: Backup regulator ready
Set by hardware to indicate that the Backup Regulator is ready.
0: Backup Regulator not ready
1: Backup Regulator ready
Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: V
1: V
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR_CR register.
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in
the PWR_CR register.
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the
or power reset.
is higher than the PVD threshold selected with the PLS[2:0] bits.
DD
is lower than the PVD threshold selected with the PLS[2:0] bits.
DD
Standby or reset until the PVDE bit is set.
EWUP bit) when the WKUP pin level is already high.
RM0401 Rev 3
Power controller (PWR)
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