Iwdg Register Map; Table 80. Iwdg Register Map And Reset Values - ST STM32F410 Reference Manual

RM0401
Note: If several reload values or prescaler values are used by application, it is mandatory to wait
until RVU bit is reset before changing the reload value and to wait until PVU bit is reset
before changing the prescaler value. However, after updating the prescaler and/or the
reload value it is not necessary to wait until RVU or PVU is reset before continuing code
execution (even in case of low-power mode entry, the write operation is taken into account
and will complete)
20.4.5

IWDG register map

The following table gives the IWDG register map and reset values.
Offset Register
IWDG_KR
0x00
Reset value
IWDG_PR
0x04
Reset value
IWDG_RLR
0x08
Reset value
IWDG_SR
0x0C
Reset value
Refer to

Table 80. IWDG register map and reset values

Section 2.2 on page 41
0 0
for the register boundary addresses.
RM0401 Rev 3
Independent watchdog (IWDG)
KEY[15:0]
0 0 0 0 0 0 0 0 0
RL[11:0]
1 1 1 1 1 1 1
0 0 0 0 0
PR[2:0]
0 0 0
1 1 1 1 1
0 0
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