Serial peripheral interface/ inter-IC sound (SPI/I2S)
The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to
reach the desired frequency, the linear divider needs to be programmed according to the
formulas below:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
f
= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
f
= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
f
= I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
f
= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
Table 126
Note:
Other configurations are possible that allow optimum clock precision.
SYSCLK
(MHz)
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
714/771
provides example precision values for different clock configurations.
Table 126. Audio-frequency precision using standard 8 MHz HSE
Data
I2SDIV
length
16
8
32
4
16
15
32
8
16
17
32
8
16
23
32
11
16
34
32
17
16
47
32
23
16
68
32
34
16
94
32
47
16
2
32
2
16
2
32
2
16
3
32
3
16
4
Target f
I2SODD
MCLK
0
No
0
No
1
No
0
No
0
No
1
No
1
No
1
No
0
No
0
No
0
No
1
No
0
No
0
No
0
No
0
No
0
Yes
0
Yes
0
Yes
0
Yes
0
Yes
0
Yes
1
Yes
RM0401 Rev 3
S
Real f
(KHz)
S
(Hz)
96000
93750
96000
93750
48000
48387.0968
48000
46875
44100
44117.647
44100
44117.647
32000
31914.8936
32000
32608.696
22050
22058.8235
22050
22058.8235
16000
15957.4468
16000
15957.447
11025
11029.4118
11025
11029.412
8000
7978.7234
8000
7978.7234
48000
46875
48000
46875
44100
46875
44100
46875
32000
31250
32000
31250
22050
20833.333
RM0401
(1)
Error
2.3438%
2.3438%
0.8065%
2.3438%
0.0400%
0.0400%
0.2660%
1.9022%
0.0400%
0.0400%
0.2660%
0.2660%
0.0400%
0.0400%
0.2660%
0.2660%
2.3430%
2.3430%
6.2925%
6.2925%
2.3438%
2.3438%
5.5178%
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