Dac Channel Enable; Single Mode Functional Description; Dac Data Format; Dac Channel Conversion - ST STM32F410 Reference Manual

RM0401
The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the
DAC_CR register.
12.4

DAC channel enable

The DAC channel can be powered on by setting the EN1 bit in the DAC_CR register. The
DAC channel is then enabled after a startup time t
Note: The EN1 bit enables the analog DAC Channel macrocell only. The DAC Channel digital
interface is enabled even if the EN1 bit is reset.
12.5

Single mode functional description

12.5.1

DAC data format

There are three possibilities:
• 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits
(stored into the DHRx[11:4] bits)
•
12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits
(stored into the DHRx[11:0] bits)
•
12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits
(stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memory-
mapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.
12.5.2

DAC channel conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three PCLK clock cycles later.

Figure 41. Data registers in single DAC channel mode

RM0401 Rev 3
Digital-to-analog converter (DAC)
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