Rcc Dedicated Clocks Configuration Register 2 (Rcc_Dckcfgr2) - ST STM32F410 Reference Manual

Reset and clock control (RCC)
5.3.18

RCC dedicated Clocks Configuration Register 2 (RCC_DCKCFGR2)

Address offset: 0x94
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
LPTIM1SEL Res. Res.
rw rw
15 14 13 12
Res. Res. Res. Res.
Bits 31:30 LPTIMSEL: LPTIM1 kernel clock source selection
Bits 29:24 Reserved, must be kept at reset value.
Bits 23:22 I2C4SEL: I2C4 kernel clock source selection
Bits 21: 0 Reserved, must be kept at reset value.
132/771
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
Set and reset by software to select the LPTIM1 clock source.
00: LPTIM1 clock = APB clock
01: LPTIM1 clock = HSI clock
10: LPTIM1 clock = LSI clock
11: LPTIM1 clock = LSE clock
Set and reset by software to select the I2C4 clock source.
00 and 11: I2C4 clock = APB clock
01: I2C4 clock = system clock
10: I2C4 clock = HSI clock
24 23 22 21
Res. I2C4SEL Res.
rw rw
8 7 6
Res. Res. Res. Res.
RM0401 Rev 3
20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. Res.
RM0401
17 16
Res. Res.
1 0
Res. Res.