Tim9 Counter (Timx_Cnt); Tim9 Prescaler (Timx_Psc); Tim9 Auto-Reload Register (Timx_Arr); Table 66. Output Control Bit For Standard Ocx Channels - ST STM32F410 Reference Manual

General-purpose timers (TIM9 and TIM11)
CCxE bit
0
1
Note: The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
16.4.8

TIM9 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000 0000
15 14 13
rw rw rw
Bits 15:0 CNT[15:0]: Counter value
16.4.9

TIM9 prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
16.4.10

TIM9 auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
422/771

Table 66. Output control bit for standard OCx channels

Output disabled (OCx='0', OCx_EN='0')
OCx=OCxREF + Polarity, OCx_EN='1'
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded into the active prescaler register at each update event.
12 11 10 9
rw rw rw rw
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 16.3.1: Time-base unit
The counter is blocked while the auto-reload value is null.
OCx output state
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
CK_PSC
8 7 6
ARR[15:0]
rw rw rw
for more details about ARR update and behavior.
RM0401 Rev 3
5 4 3 2
rw rw rw rw
5 4 3 2
rw rw rw rw
/ (PSC[15:0] + 1).
5 4 3 2
rw rw rw rw
RM0401
1 0
rw rw
1 0
rw rw
1 0
rw rw