I 2 C Interrupts; Table 103. I2C Interrupt Requests - ST STM32F410 Reference Manual

RM0401
•
A PECERR error flag/interrupt is also available in the I2C_SR1 register.
•
If DMA and PEC calculation are both enabled:-
–
–
•
To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
•
PEC calculation is corrupted by an arbitration loss.
2
23.4 I C interrupts
The table below gives the list of I
Start bit sent (Master)
Address sent (Master) or Address matched (Slave)
10-bit header sent (Master)
Stop received (Slave)
Data byte transfer finished
Receive buffer not empty
Transmit buffer empty
Bus error
Arbitration loss (Master)
Acknowledge failure
Overrun/Underrun
PEC error
Timeout/Tlow error
SMBus Alert
Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt
channel.
BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the
same interrupt channel.
be set before the ACK of the CRC reception in slave mode. It must be set when
the ACK is set low in master mode.
In transmission: when the I
controller, it automatically sends a PEC after the last byte.
In reception: when the I
controller, it will automatically consider the next byte as a PEC and will check it. A
DMA request is generated after PEC reception.
Table 103. I
Interrupt event
Inter-integrated circuit (I
2
C interface receives an EOT signal from the DMA
2
C interface receives an EOT_1 signal from the DMA
2
C interrupt requests.
2
C Interrupt requests
Event flag
ADDR
ADD10
STOPF
BTF
RxNE
BERR
ARLO
OVR
PECERR
TIMEOUT
SMBALERT
RM0401 Rev 3
Enable control bit
SB
ITEVFEN
ITEVFEN and ITBUFEN
TxE
AF
ITERREN
2
C) interface
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