ST STM32F410 Reference Manual page 389

RM0401
Offset Register
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value
0x30 Reserved
TIMx_CCR1
0x34
Reset value
TIMx_CCR2
0x38
Reset value
TIMx_CCR3
0x3C
Reset value
TIMx_CCR4
0x40
Reset value
0x44 Reserved
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
TIM5_OR
0x50
Reset value
Refer to
Table 64. TIM5 register map and reset values (continued)
ARR[31:16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR1[31:16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR2[31:16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR3[31:16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCR4[31:16]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Section 2.2 on page 41
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
for the register boundary addresses.
RM0401 Rev 3
General-purpose timers (TIM5)
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
IT4_
RMP
0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0
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