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System configuration controller (SYSCFG)
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 READY: Compensation cell ready flag
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 CMP_PD: Compensation cell power-down
7.2.9
Compensation cell control register (SYSCFG_CFGR)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 FMPI2C4_SDA
Bit 0 FMPI2C4_SCL
160/771
0: I/O compensation cell not ready
1: O compensation cell ready
0: I/O compensation cell power-down mode
1: I/O compensation cell enabled
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
FMPI2C4_SDA pin selected through GPIO port mode register and GPIO alternate
function selection bits.
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
FMPI2C4_SCL pin selected through GPIO port mode register and GPIO alternate
function selection bits.
RM0401 Rev 3
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0401
19
18
17
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
FMPI2C4
FMPI2C4_
Res.
Res.
_SDA
rw
16
Res.
Res.
0
SCL
rw
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