Figure 109. Counter Timing Diagram, Internal Clock Divided By N; Figure 110. Counter Timing Diagram, Update Event - ST STM32F410 Reference Manual

Advanced arm-based 32-bit mcus
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General-purpose timers (TIM5)
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
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Figure 109. Counter timing diagram, internal clock divided by N

Figure 110. Counter timing diagram, Update event

RM0401 Rev 3
RM0401

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