Table 19. Stop Operating Modes - ST STM32F410 Reference Manual

Power controller (PWR)
When the code is executed from internal SRAM and the Flash memory is configured in low-
power mode before entering Stop mode, the Flash memory stays in low-power mode after
waking up from Stop. In this case, only the HSI RC clock startup time and the regulator
wakeup time apply.
Stop mode MRLV bit
STOP MR
STOP MRFPD
STOP LP
STOP LPFPD
STOP MRLV
STOP LPLV
Entering Stop mode
The Stop mode is entered according to
SLEEPDEEP bit in the Cortex
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
The following features can be selected by programming individual control bits before
entering Stop mode:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
80/771

Table 19. Stop operating modes

LPLV bit
0 -
0 -
0 0
- 0
1 -
- 1
®
Table 20 for details on how to enter the Stop mode.
FPDS bit LPDS bit
0 0
1 0
0 1
1 1
- 0
- 1
Section : Entering low-power
-M4 with FPU System Control register is set.
RM0401 Rev 3
Wakeup latency
HSI RC startup time
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode
HSI RC startup time +
regulator wakeup time from LP mode
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode +
regulator wakeup time from LP mode
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode +
Main regulator from low voltage mode
HSI RC startup time +
Flash wakeup time from Deep Power
Down mode +
regulator wakeup time from Low
Voltage LP mode
mode, when the
PWR power control register
RM0401