Fmpi2C Slave Mode; Table 89. Fmpi2C Configuration - ST STM32F410 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
When RELOAD=0 in master mode, the counter can be used in 2 modes:
•
Automatic end mode (AUTOEND = '1' in the FMPI2C_CR2 register). In this mode, the
master automatically sends a STOP condition once the number of bytes programmed
in the NBYTES[7:0] bit field has been transferred.
• Software end mode (AUTOEND = '0' in the FMPI2C_CR2 register). In this mode,
software action is expected once the number of bytes programmed in the NBYTES[7:0]
bit field has been transferred; the TC flag is set and an interrupt is generated if the
TCIE bit is set. The SCL signal is stretched as long as the TC flag is set. The TC flag is
cleared by software when the START or STOP bit is set in the FMPI2C_CR2 register.
This mode must be used when the master wants to send a RESTART condition.
Caution: The AUTOEND bit has no effect when the RELOAD bit is set.
Master Tx/Rx NBYTES + STOP
Master Tx/Rx + NBYTES + RESTART
all received bytes ACKed
Slave Rx with ACK control
22.4.8

FMPI2C slave mode

FMPI2C slave initialization
In order to work in slave mode, the user must enable at least one slave address. Two
registers FMPI2C_OAR1 and FMPI2C_OAR2 are available in order to program the slave
own addresses OA1 and OA2.
•
OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by
setting the OA1MODE bit in the FMPI2C_OAR1 register.
OA1 is enabled by setting the OA1EN bit in the FMPI2C_OAR1 register.
•
If additional slave addresses are required, the 2nd slave address OA2 can be
configured. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in
the FMPI2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only
OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the
received address. As soon as OA2MSK is not equal to 0, the address comparator for
OA2 excludes the FMPI2C reserved addresses (0000 XXX and 1111 XXX), which are
not acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged
(except reserved addresses). OA2 is always a 7-bit address.
These reserved addresses can be acknowledged if they are enabled by the specific
enable bit, if they are programmed in the FMPI2C_OAR1 or FMPI2C_OAR2 register
with OA2MSK=0.
OA2 is enabled by setting the OA2EN bit in the FMPI2C_OAR2 register.
• The General Call address is enabled by setting the GCEN bit in the FMPI2C_CR1
register.
When the FMPI2C is selected by one of its enabled addresses, the ADDR interrupt status
flag is set, and an interrupt is generated if the ADDRIE bit is set.
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Table 89. FMPI2C configuration

Function
Slave Tx/Rx
RM0401 Rev 3
SBC bit RELOAD bit
x 0
x 0
0 x
1 1
RM0401
AUTOEND bit
1
0
x
x