Rcc Clock Interrupt Register (Rcc_Cir) - ST STM32F410 Reference Manual

RM0401
5.3.4

RCC clock interrupt register (RCC_CIR)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
15 14 13 12
PLL
Res. Res. Res.
RDYIE
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
Bits 22:21 Reserved, must be kept at reset value.
Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
Bit 19 HSERDYC: HSE ready interrupt clear
Bit 18 HSIRDYC: HSI ready interrupt clear
Bit 17 LSERDYC: LSE ready interrupt clear
Bit 16 LSIRDYC: LSI ready interrupt clear
Bits 15:13 Reserved, must be kept at reset value.
27 26 25
Reserved
11 10 9
HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
24 23 22
CSSC Res.
w
8 7 6
LSI
CSSF Res.
RDYIE
rw r
RM0401 Rev 3
Reset and clock control (RCC)
21 20 19 18
PLL HSE HSI
Res.
RDYC RDYC RDYC
w w w
5 4 3 2
PLL HSE HSI
Res.
RDYF RDYF RDYF
r r r
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r
109/771
134