ST STM32F410 Reference Manual page 134

Reset and clock control (RCC)
Addr. Register
offset name
RCC_AHB1L
0x50
PENR
0x54 to
0x5C
RCC_APB1L
0x60
PENR
RCC_APB2L
0x64
PENR
0x68 to
0x6C
0x70 RCC_BDCR
0x74 RCC_CSR
0x78 to
0x7C
0x80 RCC_SSCGR
0x84 to
0x88
RCC_
0x8C
DCKCFGR
0x90
RCC_
0x94
DCKCFGR2
Refer to
134/771
Table 23. RCC register map and reset values (continued)
Section 2.2: Memory organization
Reserved
Reserved
Reserved
INCSTEP
Reserved
Reserved
for the register boundary addresses.
RM0401 Rev 3
RM0401
MODPER