ST STM32F410 Reference Manual page 75

RM0401
In addition, the power consumption in Run mode can be reduced by one of the following
means:
•
Optimizing PLL VCO frequency (see
•
Slowing down the system clocks (see
•
Gating the clocks to the APBx and AHBx peripherals when they are unused (see
Section 4.3.3: Peripheral clock
• Configuring the Flash memory in low-power mode (Stop or Deep-power down) to
execute code from RAM (see
execution from
Entering low-power mode
Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex
FPU System Control register is set on Return from ISR.
Entering low-power mode through WFI or WFE is executed only is no interrupt or no event is
pending.
Exiting low-power mode
The MCU exits from Sleep and Stop modes low-power mode depending on the way the low-
power mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
• If the WFE instruction is used to enter the low-power mode, the MCU exits the low-
power mode as soon as an event occurs. The wakeup event can be generated either
by:
–
–
The MCU exits from Standby low-power mode through an external reset (NRST pin), an
IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see
Figure 176: RTC block
RAM).
NVIC IRQ interrupt:
When SEVONPEND = 0 in the Cortex
enabling an interrupt in the peripheral control register and in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC
peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register)
have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and
interrupt the MCU.
When SEVONPEND = 1 in the Cortex
enabling an interrupt in the peripheral control register and optionally in the NVIC.
When the MCU resumes from WFE, the peripheral interrupt pending bit and when
enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear
pending register) have to be cleared. All NVIC interrupts will wakeup the MCU,
even the disabled ones.Only enabled NVIC interrupts with sufficient priority will
wakeup and interrupt the MCU.
Event
This is done by configuring a EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bits corresponding to the event
line is not set. It may be necessary to clear the interrupt flag in the peripheral.
diagram).
Section 4.3.1: Optimizing PLL VCO
Section 4.3.2: Slowing down system
gating)
Section 4.3.4: Flash memory in low-power mode for code
®
-M4 with FPU System Control register: by
®
-M4 with FPU System Control register: by
RM0401 Rev 3
Power controller (PWR)
frequency)
clocks)
®
-M4 with
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